index - Equipe Secure and Safe Hardware Accéder directement au contenu

 

Dernières publications

Chargement de la page

Mots clés

Security and privacy Authentication AES Neural networks Randomness Variance-based Power Attack VPA Aging Switches Electromagnetic CPA Dual-rail with Precharge Logic DPL Receivers Application-specific VLSI designs Loop PUF Side-channel analysis 3G mobile communication Security Differential power analysis DPA Formal methods Writing Sensors Machine learning Formal proof FDSOI Power demand Side-Channel Analysis SCA Hardware Protocols Fault injection attack Convolution Field programmable gate arrays Signal processing algorithms Asynchronous Information leakage Temperature sensors Image processing Cryptography MRAM SCA Voltage Hardware security CRT Side-channel attack Sécurité Security services Dynamic range Reverse engineering Simulation Lightweight cryptography PUF Side-channel attacks OCaml Magnetic tunneling TRNG Random access memory Countermeasure Resistance Logic gates RSA Countermeasures Robustness Coq Tunneling magnetoresistance Steadiness Costs Elliptic curve cryptography Transistors Differential Power Analysis DPA Linearity Field Programmable Gates Array FPGA Intrusion detection Training Masking countermeasure GSM Confusion coefficient DRAM SoC Filtering Side-Channel Attacks Internet of Things Routing Mutual Information Analysis MIA Side-Channel Analysis Process variation Magnetic tunnel junction STT-MRAM Side-channel attacks SCA Estimation Computational modeling FPGA Energy consumption Power-constant logic Spin transfer torque Masking Reverse-engineering Reliability Circuit faults Fault injection ASIC Defect modeling

 

Documents avec texte intégral

Chargement de la page

Références bibliographiques

Chargement de la page

Open access

Chargement de la page

Collaborations